Flash memories are high-density nonvolatile semiconductor memories offering fast access times. Compared to other nonvolatile semiconductor memories such as conventional EPROMs or EEPROMs, flash memories are most suitable for applications wherein there are expected frequent write and read operations. Because of its light weight compared to magnetic memories such as hard disk or floppy disk memories, flash memory has a tremendous potential in the consumer electronics market. With the rapid growth of digital cameras and the desire for light-weight notebook PCs, the demand for even higher density flash memories is ever increasing.
FIG. 1A shows a top view cell layout of a typical flash memory, and FIGS. 1B and 1C are illustrative schematic diagrams of the flash memory cell along lines B-B' and C-C', respectively. The flash memory cell contains a semiconductor substrate 1, which typically is a P-type silicon substrate with a doping level ranging from 5 to 50 ohm-cm. Within the substrate 1, there are source region 2, typically an N-doped silicon, a drain region 3, also an N-doped silicon, and a channel region 4 between the source region 2 and the drain region 3. A tunnel oxide layer 5 is disposed over the channel region and the source and drain regions. Disposed over the tunnel oxide layer are one or more floating gate (poly-1), which, as shown in FIG. 1C, is positioned over a portion of the source region 2 and over a portion of the channel region 4. An insulating layer 6, which can be silicon dioxide, silicon nitride, or silicon oxynitride, is disposed covering the floating gate. A control gate is then disposed which covers a portion of the floating gate and a portion of the channel region. During an erase operation, a ground potential is applied to the drain and the source regions, and a high positive voltage is applied to the control gate. The positive charge on the control gate causes charges, if any, on the floating gate to be induced through the so-called Fowler-Nordheim tunneling mechanism to tunnel through the insulating layer 6 to the control gate, allowing the floating gate to be discharged.
To maximize the Fowler-Nordheim tunneling effect, sharp corners are formed at the edge of the floating gate. The sharp corners are created by selectively forming poly oxide only in the floating gate region during one of the photolithographic processes implemented in fabricating the flash memory cell. FIGS. 2A and 2B show the longitudinal and transverse views, respective, of the memory cell during the fabrication process, wherein the poly oxide layer is formed on top of the floating gate, using the nitride layer as a mask. However, primarily due to the stress exerted at the edge of the nitride layer, often defects in such oxide layer will be created near the sharp corner neighborhood of the floating gate, causing charges to be trapped in the oxide defects at the sharp corner and the resultant degradations in the erase efficiency. The flash memory cells with defective poly oxide often shows poor cycling performance, primarily due to erase failure.
U.S. Pat. Nos. 5,045,488, 5,067,1078, 5,202,850, and 5,278,087 disclose a single transistor electrically programmable and erasable memory cell having a second insulating layer with atop wall portion over the floating gate and a side wall portion immediately adjacent to the floating gate and has a thickness which permits the Fowler-Nordheim tunneling or charges therethrough. However, these patents never taught or suggested the existence of the defects in the oxide layer near the sharp corner neighborhood of the floating gate as mentioned above which can result in degradations in the erase efficiency of the memory cell, and, in turn, degradations in the cycling performance.